In a new video, published on Sony’s YouTube channel, members of Sony Semiconductor Solutions (SSS) group break down the technology behind a new 2-Layer Transistor Pixel stacked CMOS image sensor SSS recently announced in December 2021 at the IEEE International Electron Devices Meeting. While the first half of the video focuses on the Sony a1 and the stacked CMOS sensor used inside of it, the second half of the video dives into the novel sensor design SSS has developed, starting at roughly the 5:45 mark of the video above.
It’s here when Keiichi Nakazawa, a member of SSS’ Second Research Division who’s currently in charge of research and development for image sensors for mobile products, discusses the differences between the photodiodes in traditional stacked CMOS sensors compared to SSS’ new 2-Layer Transistor Pixel. In short, whereas traditional CMOS image sensors’ photodiodes and pixel transistors occupy the same substrate layer, this new design separates the photodiodes and pixel transistors into two different substrate layers. By splitting the layers, the photodiode can be larger, resulting in a higher signal saturation level (also referred to as full well capacity), while the larger transistors result in less noise. This outcome is a two-fold benefit that both increases dynamic range while decreasing noise.
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| Stacked CMOS image sensor architectures. Image credit: Sony |
From an engineering and manufacturing perspective, the 2-Layer Transistor Pixel design requires nanometer-level precision for arranging the photodiodes and pixel transistors. Sony adopted a 3D sequential integration process instead of conventional bonding of completed wafers. After the photodiode is formed, two layers are bonded together and then the photodiode is used to line up the creation of the transistor in the second layer. As Nakazawa puts it, alignment accuracy is determined by the lithography rather than the bonding.
The process includes its own challenges, including heat in the production process after stacking the wafers. Whereas traditional CMOS sensor production requires heat resistance of around 400° C, the new design requires a much higher heat resistance of over 1,000° C. To address the problem, Sony developed new bonding technology and built its transistors to adapt.
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| Image credit: Sony |
By separating the photodiode and the transistor pixel for each photosite, Sony’s engineers were able to optimize the components separately, resulting in improved noise performance and dynamic range. Beyond image quality, the new design promises other improvements, which the R&D team is working on.
While new information was somewhat light in the Sony Semiconductor Solutions video, it’s always interesting to hear from some of the enthusiastic and passionate engineers behind the latest and greatest in image sensor technology. It will be fascinating to see when Sony’s new 2-Layer Transistor Pixel stacked image sensor makes its way into consumer products and what sort of performance it offers. And as always, we can’t wait to see what’s next for Sony’s full-frame Alpha cameras.
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This article comes from DP Review and can be read on the original site.
